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amplifier","url":"https://pages.dcaclab.com/experiments/75254-common-collector-emitter-follower-amplifier","id":75254},{"opened":false,"text":"RL Series Circuit1","url":"https://pages.dcaclab.com/experiments/75229-rl-series-circuit1","id":75229},{"opened":false,"text":"RL Series Circuit","url":"https://pages.dcaclab.com/experiments/75121-rl-series-circuit-9","id":75121},{"opened":false,"text":"Voltage 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OptoCoupler","public":true,"user_id":200061,"created_at":"2025-05-19T17:11:14.622Z","updated_at":"2025-05-19T17:12:24.608Z","official":false},{"id":134,"name":"74HC07","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_6A","right-2":"Out_6","right-3":"In_5A","right-4":"Out_5","right-5":"In_4A","right-6":"Out_4","left-0":"Gnd","left-1":"Out_3","left-2":"In_3A","left-3":"Out_2","left-4":"In_2A","left-5":"Out_1","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC07 In_1A Out_1 In_2A Out_2 In_3A Out_3 Gnd Out_4 In_4A Out_5 In_5A Out_6 In_6A Vcc * 74HC07 Hex Buffer/Driver with Open-Drain Outputs .subckt 74HC07 In_1A Out_1 In_2A Out_2 In_3A Out_3 Gnd Out_4 In_4A Out_5 In_5A Out_6 In_6A Vcc * Each buffer modeled using a MOSFET for open-drain behavior and a logic-controlled switch * You may replace behavioral models with transistor-level models if needed * Buffer 1 XBUF1 In_1A Out_1 Gnd Vcc HC07BUF * Buffer 2 XBUF2 In_2A Out_2 Gnd Vcc HC07BUF * Buffer 3 XBUF3 In_3A Out_3 Gnd Vcc HC07BUF * Buffer 4 XBUF4 In_4A Out_4 Gnd Vcc HC07BUF * Buffer 5 XBUF5 In_5A Out_5 Gnd Vcc HC07BUF * Buffer 6 XBUF6 In_6A Out_6 Gnd Vcc HC07BUF .ends 74HC07 * Define a subcircuit for a single open-drain buffer (HC07BUF) .subckt HC07BUF A Y GND VCC * Behavioral logic control: Pull-down NMOS when input is high * Assume VCC = 5V typical M1 Y GND GND GND NMOS E1 N1 0 VALUE = { V(A) > 2.0 ? 1 : 0 } S1 Y GND N1 GND SW_NMOS .model NMOS NMOS (VTO=1.5 BETA=1m) .model SW_NMOS VSWITCH (RON=10 ROFF=1Meg VON=1 VOFF=0.5) .ends HC07BUF ","description":"Hex Buffer with Open-Drain","public":true,"user_id":200061,"created_at":"2025-05-19T16:57:29.925Z","updated_at":"2025-05-19T17:30:37.001Z","official":false},{"id":133,"name":"74HC86","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC86 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC86 Quad 2-Input XOR Gate .SUBCKT 74HC86 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 EXOR1 Out_1 0 VALUE = { IF((V(In_1A)>3.5 && V(In_1B)<1.5) || (V(In_1A)<1.5 && V(In_1B)>3.5), 5, 0) } * Gate 2 EXOR2 Out_2 0 VALUE = { IF((V(In_2A)>3.5 && V(In_2B)<1.5) || (V(In_2A)<1.5 && V(In_2B)>3.5), 5, 0) } * Gate 3 EXOR3 Out_3 0 VALUE = { IF((V(In_3A)>3.5 && V(In_3B)<1.5) || (V(In_3A)<1.5 && V(In_3B)>3.5), 5, 0) } * Gate 4 EXOR4 Out_4 0 VALUE = { IF((V(In_4A)>3.5 && V(In_4B)<1.5) || (V(In_4A)<1.5 && V(In_4B)>3.5), 5, 0) } .ENDS 74HC86 ","description":"Quad 2-input XOR","public":true,"user_id":200061,"created_at":"2025-05-19T16:56:09.230Z","updated_at":"2025-05-19T17:15:04.175Z","official":false},{"id":132,"name":"74HC02","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC02 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC02 Quad 2-Input NOR Gate Behavioral Model * Inputs: In_xA, In_xB (logic inputs) * Outputs: Out_x (logic output) * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC02 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 ENOR1 Out_1 0 VALUE = { IF(V(In_1A)<1.5 && V(In_1B)<1.5, 5, 0) } * Gate 2 ENOR2 Out_2 0 VALUE = { IF(V(In_2A)<1.5 && V(In_2B)<1.5, 5, 0) } * Gate 3 ENOR3 Out_3 0 VALUE = { IF(V(In_3A)<1.5 && V(In_3B)<1.5, 5, 0) } * Gate 4 ENOR4 Out_4 0 VALUE = { IF(V(In_4A)<1.5 && V(In_4B)<1.5, 5, 0) } .ENDS 74HC02 ","description":"Quad 2-input NOR","public":true,"user_id":200061,"created_at":"2025-05-19T16:55:37.090Z","updated_at":"2025-05-19T17:17:01.934Z","official":false},{"id":110,"name":"74HC32","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC32 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC32 Quad 2-Input OR Gate Behavioral Model * Inputs: In_xA, In_xB * Outputs: Out_x * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC32 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 E1 Out_1 0 VALUE = { IF(V(In_1A)>1.5 || V(In_1B)>1.5, 5, 0) } * Gate 2 E2 Out_2 0 VALUE = { IF(V(In_2A)>1.5 || V(In_2B)>1.5, 5, 0) } * Gate 3 E3 Out_3 0 VALUE = { IF(V(In_3A)>1.5 || V(In_3B)>1.5, 5, 0) } * Gate 4 E4 Out_4 0 VALUE = { IF(V(In_4A)>1.5 || V(In_4B)>1.5, 5, 0) } .ENDS 74HC32 ","description":"Quad 2-input OR","public":true,"user_id":200061,"created_at":"2025-05-12T20:19:19.800Z","updated_at":"2025-05-19T17:18:13.950Z","official":false},{"id":109,"name":"74HC08","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":[]},"netlist":".subckt 74HC08 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC08 Quad 2-Input AND Gate Behavioral Model * Inputs: In_xA, In_xB * Outputs: Out_x * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC08 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 E1 Out_1 0 VALUE = { IF(V(In_1A)>1.5 && V(In_1B)>1.5, 5, 0) } * Gate 2 E2 Out_2 0 VALUE = { IF(V(In_2A)>1.5 && V(In_2B)>1.5, 5, 0) } * Gate 3 E3 Out_3 0 VALUE = { IF(V(In_3A)>1.5 && V(In_3B)>1.5, 5, 0) } * Gate 4 E4 Out_4 0 VALUE = { IF(V(In_4A)>1.5 && V(In_4B)>1.5, 5, 0) } .ENDS 74HC08 ","description":"Quad 2-input AND","public":true,"user_id":200061,"created_at":"2025-05-12T20:14:24.416Z","updated_at":"2025-05-19T20:18:11.018Z","official":false},{"id":54,"name":"74HC00","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC00 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC00 Quad 2-Input NAND Gate Behavioral Model * Inputs: In_xA, In_xB * Outputs: Out_x * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC00 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 EN1 Out_1 0 VALUE = { IF(V(In_1A)>1.5 && V(In_1B)>1.5, 0, 5) } * Gate 2 EN2 Out_2 0 VALUE = { IF(V(In_2A)>1.5 && V(In_2B)>1.5, 0, 5) } * Gate 3 EN3 Out_3 0 VALUE = { IF(V(In_3A)>1.5 && V(In_3B)>1.5, 0, 5) } * Gate 4 EN4 Out_4 0 VALUE = { IF(V(In_4A)>1.5 && V(In_4B)>1.5, 0, 5) } .ENDS 74HC00 ","description":"Quad 2-input NAND","public":true,"user_id":200061,"created_at":"2025-04-16T17:34:31.881Z","updated_at":"2025-05-19T17:19:37.969Z","official":false}],"official_ics":[{"id":4,"name":"LM317","vertical_pins":0,"horizontal_pins":3,"pin_labels":{"top-0":"","top-1":"","top-2":"","bottom-0":"in","bottom-1":"out","bottom-2":"adj"},"netlist":".subckt LM317 in out adj Q2 5 5 6 QPL .1 Q3 5 8 9 QNL .2 Q4 8 5 7 QPL .1 Q5 81 8 out QNL .2 Q6 out 81 10 QPL .2 Q7 12 81 13 QNL .2 *Q8 10 5 11 QPL .2 Q8 10A 5 11 QPL .2 Q9 14 12 10 QPL .2 Q10 16 5 17 QPL .2 Q11 16 14 15 QNL .2 OFF Q12 out 20 16 QPL .2 Q13 in 19 20 QNL .2 Q14 19 5 18 QPL .2 Q15 out 21 19 QPL .2 Q16 21 22 16 QPL .2 Q17 21 out 24 QNL .2 Q18 22 22 16 QPL .2 Q19 22 out 241 QNL .2 Q20 out 25 16 QPL .2 Q21 25 26 out QNL .2 Q22A 35 35 in QPL .2 Q22B 16 35 in QPL .2 Q23 35 16 30 QNL .2 Q24A 27 40 29 QNL .2 Q24B 27 40 28 QNL .2 Q25 in 31 41 QNL 5 Q26 in 41 32 QNL 50 D1 out 4 DZ D2 33 in DZ D3 29 34 DZ R1 in 6 310 R2 in 7 310 R3 in 11 190 R4 in 17 82 R5 in 18 5.6K R6 4 8 100K R7 8 81 130 *R8 10 12 12.4K R8 10A 12 12.4K R9 9 out 180 R10 13 out 4.1K R11 14 out 5.8K R12 15 out 72 R13 20 out 5.1K R14 adj 24 12K R15 24 241 2.4K R16 16 25 6.7K R17 16 40 12K R18 30 41 130 R19 16 31 370 R20 26 27 13K R21 27 40 400 R22 out 41 160 R23 33 34 18K R24 28 29 160 R25 28 32 3 R26 32 out .1 C1 21 out 30PF C2 21 adj 30PF C3 25 26 5PF CBS1 5 out 2PF CBS2 35 out 1PF CBS3 22 out 1PF .MODEL JN NJF (BETA=1E-4 VTO=-7) .MODEL DZ D(BV=6.3) .MODEL QNL NPN (EG=1.22 BF=80 RB=100 CCS=1.5PF TF=.3NS TR=6NS + CJE=2PF CJC=1PF VAF=100 IS=1E-22 NF=1.2) .MODEL QPL PNP (BF=40 RB=20 TF=.6NS TR=10NS CJE=1.5PF CJC=1PF VAF=50 + IS=1E-22 NF=1.2) .ENDS LM317/TI","description":"","public":true,"user_id":1953,"created_at":"2025-04-01T06:52:09.037Z","updated_at":"2025-04-05T10:50:30.480Z","official":true},{"id":1,"name":"555","vertical_pins":4,"horizontal_pins":0,"pin_labels":{"right-0":"VCC","right-1":"DISCH","right-2":"THRSH","right-3":"CONT","left-0":"RESET","left-1":"OUT","left-2":"TRIGGER","left-3":"GND","initial_checked":["right-2"]},"netlist":".subckt 555 GND TRIGGER OUT RESET CONT THRSH DISCH VCC * Version 2 using generic OpAmp model from the forum. * Now supports output voltage set by Vcc Pin. * This is mostly a timing model and may not be DC accurate in all cases. * credit: https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/f535c0f1b9/ * Pin mapping: * GND * TRIGGER * OUT * RESET * CONT * THRSH * DISCH * VCC R1 VCC CONT 5000 R2 CONT 10 5000 R3 10 GND 5000 X1 THRSH CONT VCC 0 11 genopa1 ; the reset comparator X2 10 TRIGGER VCC 0 12 genopa1 ; the set comparator * R S R S abridge [11 12] [22 21] adc_buff ; bridge from comparators to set/reset controls a0 z1 pulldown1 ; pull-down for unused clock and data * data clock set reset q qbar a1 z1 z1 21 25 23 24 flop1 ; the flip-flop abridge1 [24] [13] dac1 ; bridge qbar to discharge timing cap, turn on Q1 abridge2 [24] [26] dac1 ; bridge qbar to pseudo tristate driver Q1 DISCH 13 GND N ; the discharge transistor * Active low master reset from pin RESET abridge3 [RESET] [30] adc_buff a2 30 31 inv1 a3 [22 31] 25 or1 ; Reset when external reset is asserted or comparator trips * Make the Q output of the flip-flop drive to VCC when driven R4 OUT VCC 100 Q2 OUT 26 0 N * Models .model adc_buff adc_bridge(in_low = 0.7 in_high = 3.0) .model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 + reset_delay = 27.0e-9 ic = 0 rise_delay = 10.0e-9 + fall_delay = 3e-9) .model pulldown1 d_pulldown(load = 20.0e-12) .model dac1 dac_bridge(out_low = 0.1 out_high = 1.0 out_undef = 2.2 + input_load = 5.0e-12 t_rise = 50e-9 + t_fall = 20e-9) .model N NPN .model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9 + input_load = 0.5e-12) .model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9 + input_load = 0.5e-12) .ends * Generic OpAmp model .subckt genopa1 in+ in- vcc vee out params: POLE=20 GAIN=20k VOFFSET=5m ROUT=10 RIN=10Meg Rin in+ in+ {RIN} Voff in+ inoff dc {VOFFSET} G10 0 int inoff in- 100u R1 int 0 {GAIN/100u} C1 int 0 {1/(6.28*(GAIN/100u)*POLE)} Eout 2 0 int 0 1 Rout 2 out {ROUT} Elow 3 0 vee 0 1 Ehigh 8 0 vcc 0 1 Dlow 3 int Dlimit Dhigh int 8 Dlimit .model Dlimit D N=0.01 .ends .end ","description":"The 555 timer is a versatile integrated circuit capable of operating in three distinct modes: 1. Astable Mode (Free-Running Oscillator) The 555 continuously generates square wave pulses without requiring external trigger pulses. The output oscillates between HIGH and LOW states indefinitely. The frequency and duty cycle are determined by external resistors (R1, R2) and a capacitor (C). This mode is ideal for generating clock signals, tone generators, and LED flashers. 2. Monostable Mode (One-Shot Timer) The 555 produces a single output pulse of a specific duration when triggered by an input pulse. After the pulse completes, the circuit returns to its stable LOW state and waits for the next trigger. This mode is perfect for precision timing applications and pulse generation. 3. Bistable Mode (Flip-Flop) The 555 acts as a latch, switching states based on separate SET and RESET inputs. The output remains in its current state until commanded to change, making it useful for toggle switches and latching circuits.","public":true,"user_id":1953,"created_at":"2025-03-29T15:05:00.797Z","updated_at":"2025-12-20T08:53:14.245Z","official":true}],"show_ic_creator":false,"is_breadboard_lab":false}